Reto Zimmermann's Home Page
Research activities
Research interests
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Digital VLSI design and synthesis
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Computer arithmetic
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Computer-aided design
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Artificial intelligence
Working position and environment
Formerly research and teaching assistant on digital VLSI design and Ph.D.
student at
Now with Synopsys Switzerland LLC,
Solutions Group, DesignWare, in Zurich, Switzerland.
Publications
Thesis
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R. Zimmermann, Binary Adder Architectures for Cell-Based VLSI and their
Synthesis, PhD thesis, Swiss Federal Institute of Technology (ETH)
Zurich, Hartung-Gorre Verlag, 1998.
[abstract,
pdf (A4),
pdf (letter),
postscript (gzip),
postscript (gzip, letter),
postscript (winzip),
postscript (winzip, letter)]
Journal papers
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R. Zimmermann and W. Fichtner, "Low-Power Logic Styles: CMOS Versus Pass-Transistor
Logic", IEEE Journal of Solid-State Circuits, vol. 32, no. 7, pp.
1079-1090, July 1997.
[abstract,
pdf,
postscript
(gzip),
postscript
(winzip)]
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R. Zimmermann, A. Curiger, H. Bonnenberg, H. Kaeslin, N. Felber, and W.
Fichtner, "A 177 Mb/s VLSI Implementation of the International Data Encryption
Algorithm", IEEE Journal of Solid-State Circuits, vol. 29, no. 3,
pp. 303-307, March 1994.
[abstract,
postscript
(gzip)]
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R. Zimmermann and H. Kaeslin, "Cell-Based Multilevel Carry-Increment Adders
with Minimal AT- and PT-Products", tried to publish in IEEE Transactions
on VLSI Systems but resigned when having to revise it for a second
time after a review process of three years!
[abstract,
postscript
(gzip)]
Conference papers
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R. Zimmermann, "Datapath Synthesis for Standard-Cell Design", in Proc. 19th IEEE Symposium on Computer Arithmetic, Portland, Oregon, USA, June 8-10, 2009.
[abstract, pdf]
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R. Zimmermann and D. Q. Tran, "Optimized Synthesis of Sum-of-Products", in Proc. 37th Asilomar Conference on Signals, Systems and Computers, November 9-12, 2003.
[abstract, pdf]
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R. Zimmermann, "Efficient VLSI Implementation of Modulo (2^n±1)
Addition and Multiplication", in Proc. 14th IEEE Symposium on Computer
Arithmetic, Adelaide, Australia, April 14-16, 1999, pp. 158-167.
[abstract, pdf, postscript
(gzip), postscript (winzip)]
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R. Zimmermann, "VHDL Library of Arithmetic Units", in Proc. First Int.
Forum on Design Languages (FDL'98), Lausanne, Switzerland, Sept. 1998,
pp. 267-272.
[abstract, postscript
(gzip), postscript (winzip)]
-
R. Zimmermann, "Non-Heuristic Optimization and Synthesis of Parallel-Prefix
Adders", in Proc. Int. Workshop on Logic and Architecture Synthesis
(IWLAS'96), Grenoble, France, Dec. 1996, pp. 123-132.
[abstract,
postscript
(gzip),
postscript (gzip,
letter),
postscript (winzip),
postscript
(winzip, letter)]
-
R. Zimmermann and R. Gupta, "Low-Power Logic Styles : CMOS vs CPL", in
Proc.
22nd European Solid-State Circuits Conference (ESSCIRC'96), Neuchâtel,
Switzerland, Sept. 1996, pp. 112-115.
[abstract,
postscript
(gzip)]
Technical reports / lecture notes
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R. Zimmermann, Computer Arithmetic: Principles, Architectures, and VLSI
Design, Lecture notes, Integrated Systems Laboratory, ETH Zürich,
1997.
[contents,
pdf (A4),
pdf (letter),
postscript (gzip),
postscript (gzip, letter),
postscript (winzip),
postscript (winzip, letter)]
-
R. Zimmermann, "VHDL Library of Arithmetic Units", Technical report
no. 98/3, Integrated Systems Laboratory, ETH Zürich, Jan. 1998.
[abstract, postscript
(gzip), postscript (winzip)]
-
H. Kunz and R. Zimmermann, "High-Performance Adder Circuit Generators
in Parameterized Structural VHDL", Technical report no. 96/7, Integrated
Systems Laboratory, ETH Zürich, Aug. 1996.
[abstract,
postscript
(gzip),
postscript
(winzip)]
-
R. Zimmermann and M. Neeracher, "SHIVA: Correlator/Demodulator Chip
for Direct-Sequence Spread-Spectrum RAKE-Receiver", Technical report
no. 94/9, Integrated Systems Laboratory, ETH Zürich, May 1994.
[abstract, postscript
(gzip), postscript (winzip)]
Things to download
Reto Zimmermann
Synopsys Switzerland LLC
Affolternstrasse 52
CH-8050 Zurich
Switzerland
email : reto@gnu.org
www : http://www.iis.ee.ethz.ch/~zimmi/
Reto Zimmermann / May 2006 / Home
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